Bias current circuit

ABSTRACT

Circuit for producing a bias current which is inversely proportional to the common emitter forward gain (h fe ) of a transistor. It includes a first transistor and second and third transistors of opposite conductivity type to the first. The base emitter paths of the second and third transistors are connected in parallel. The first transistor has collector-to-base feedback to regulate its collector current to a prescribed value, which feedback connection is through the emitter-to-collector path of the second transistor. The bias current proportional to the prescribed value divided by the h fe  of the first transistor is provided at the collector of the third transistor.

The present invention relates to bias circuits for supplying bias currents inversely proportional to the common-emitter current gain, or h_(fe), of a transistor.

Examples of this type of bias circuit are known from U.S. Pat. Nos. 3,846,696, 3,855,541, 3,878,471, 3,887,880 and 3,891,935. Bias circuits embodying the present invention are simpler than those shown in the patents above in circumstances when it is desired to divide a prescribed input bias current by the h_(fe) of a transistor to provide a similarly directed output bias current. The bias circuit described herein is particularly suitable for supplying quiescent base bias current to an associated common-emitter amplifier transistor.

In the drawing:

FIG. 1 is a schematic diagram of a bias circuit embodying the present invention, shown biasing the base electrode of a common-emitter amplifier transistor; and

FIG. 2 is a schematic diagram of a representative alternative configuration to that shown in FIG. 1.

In FIG. 1, common-emitter amplifier transistor Q_(A) is provided quiescent base current which varies in inverse proportion to its h_(fe). This, by means of a bias circuit essentially comprising transistors Q₁, Q₂ and Q₃. Q₁ has an h_(fe) similar to that of Q_(A), which similarity is maintained despite temperature change, by virtue of Q_(A) and Q₁ being arranged to share the same thermal environment-- e.g., that of a monolithic integrated circuit chip. Q₂ and Q₃, which have parallelled base-emitter paths and are of complementary conductivity type to that of Q₁, are arranged to have proportional effective transconductance (g_(m)) characteristics and to this end may be arranged in the same thermal environment as each other and/or provided with current feedback resistors (not shown) in series with their base-emitter paths.

Q₄, Q₅ and Q₆, also of complementary conductivity type to Q₁, are connected as a dual output current mirror amplifier, CMA. The input terminal of the CMA is connected via the serial connection of resistor R₁ and diode D₁ to ground, and the common-terminal of the CMA is connected to the operating potential +V_(CC). The resultant current flow through the input circuit of the CMA, R₁, and D₁ is equal to (V_(CC) - 2V_(BE))/R₁, where V_(BE) is the offset potential across a semiconductor junction such as the base-emitter junction of self-biased transistor Q₄ or D₁, and R₁ is the resistance of resistor R₁. The first and second output terminals of the CMA at the collector electrodes of Q₅ and Q₆, respectively, respond with respective currents related as the transconductances g_(m5) and g_(m6) of Q₅ and Q₆, respectively, to the transconductance g_(m4) of Q₄. That is, Q₅ and Q₆ are each conditioned to operate as a constant current source.

Q₂ provides, by means of its common-base-amplifier action, degenerative collector-to-base feedback to Q₁ for regulating Q₁ 's collector current I_(C1) demand substantially to equal the constant current supplied from the collector electrode of Q₅. (Q₂ like any transistor, exhibits internal current feedback in carrying out common-base amplifier action, adjusting its base current to support the emitter current flow forced on it here by the collector-to-base feedback of Q₁.) Assuming the h_(fe) of Q₁ to be at least 10 or so, as is normally the case, only a relatively small portion of the constant current provided by Q₅ flows as emitter currents in Q₂ and Q₃. The emitter current of Q₂ is required to supply base current to Q₁ via the common-base amplifier action of Q₁, and a related current flows in Q₃ because of their parallelled base-emitter paths. So, the collector current I_(C2) of Q₂ is substantially equal to the collector current I_(C5) of Q₅ divided by the common-emitter current gain h_(fel) of Q₁. (I_(C2) ≃ I_(C5) /h_(fel)). Owing to the parallelled base-emitter paths of Q₂ and Q₃, the collector current of I_(C3) of Q₃ is equal to I_(C2) times the effective transconductance g_(m3) of Q₃ divided by the effective transconductance g_(m2) of Q₂. (I_(C3) = I_(C2) (g_(m3) /g_(m2)). Therefore, I_(C3) ≃ (I_(C5) /h_(fel)) (g_(m3) /g_(m2)), where g_(m3) /g_(m2) remains essentially constant during operation. The desired objective of the present invention, providing a bias circuit for providing a current which is substantially in inverse proportion to the h_(fe) of a transistor, is therefore achieved.

Applying I_(C3) as quiescent base current to Q_(A), which has the same h_(fe) as Q₁ will cause Q_(A) to demand a quiescent collector current I_(CA) that is h_(fe) times as large as its base current, equal to I_(C3). I_(CA) is therefore substantially independent of h_(fe) and can be expressed as follows. I_(CA) ≃ I_(C5) (g_(m3) /g_(m2)). If g_(m6) /g_(m5) is made equal to (g_(m3) /g_(m2)) the quiescent collector current I_(CA) demanded by Q_(A) will be met with a substantial degree of exactness by the collector current I_(C6) provided by Q₆. So, no substantial amount of quiescent current need flow through the output terminal T_(OUT) or any load connected thereto. The quiescent potential at T_(OUT) will be determined by the load connections and might, for example, be +V_(CC) /2 where the load is a resistive one connected between T_(OUT) and a +V_(CC) /2 potential.

The point to be made here is that the application of a quiescent base current to a transistor, which current is inversely proportional to the h_(fe) of the transistor results in a well-defined collector current independent of the variations with temperature otherwise attributable to its h_(fe), that would obtain from current-mode base biasing. Current-mode biasing of the base of Q_(A) --that is, biasing from a bias circuit with relatively high source impedance compared to the impedance at its base electrode--is desirable. It avoids lowering of the input impedance the input signal source S₁ "sees" at the terminal T_(IN) to which the base electrode of Q_(A) connects.

FIG. 2 shows an alternative way for controlling the value to which I_(C1) is regulated. R₁ biases D₁ into forward conduction to develop a 1V_(BE) potential offset thereacross, and the emitter follower actions of Q₂ and Q₃ tend to hold their emitter potentials at +2V_(BE). This causes a tendency for current flow of (V_(CC) - 2V_(BE))/R₂ through resistor R₂, which has a resistance R₂, which current flows primarily as I_(C1), being conducted to ground through the collector-emitter path of Q₁. Any tendency for I_(C1) to be too large reduces the base-emitter potential of Q₂, curtailing the collector current Q₂ provided to the base electrode of Q₁, thereby reducing the conduction of Q₁ and reducing I_(C1). Any tendency for I_(C1) to be too small increases the base-emitter potential of Q₂, increasing I_(C2), increasing the conduction of Q₁, and increasing I_(C1).

The operation of the FIG. 2 bias circuit is concisely stated as follows. I_(C1) ≃ (V_(CC) - 2V_(BE))R₂. I_(C2) ≃ (V_(CC) - 2V_(BE))/R₂ h_(fel). I_(C3) ≃ (g_(m3) /g_(m2)) (V_(CC) -2V_(BE))/R₂ h_(fel). As in FIG. 1, g_(m3) remains in substantially fixed proportion to g_(m2) during operation, that is, g_(m3) /g_(m2) remains essentially constant. The bias circuit of the FIGURE thus achieves the objective of providing a bias current inversely proportional to transistor h_(fe). Applied as quiescent base current to Q_(A), the following collector current I_(CA) is demanded. I_(CA) = (g_(m3) /g_(m2)) (V_(CC) - 2V_(BE))/R₂. The quiescent potential at T_(OUT) can be made (V_(CC) /2)+V_(BE), suitable for application to an emitter follower stage, for example, by making the resistance R₃ of resistor R₃ obey the following relationship. R₃ = (R₂ /2) (g_(m2) /g_(m3)).

The biasing of the base electrodes of Q₂ and Q₃ at +1V_(BE) is interesting in that it places equal potentials on the base and collector electrodes of these transistors and avoids leakage across their respective collector-base junctions, to eliminate an effect having a second order influence on the proportioning of their collector currents. The base electrodes of Q₂ and Q₃ can be biased to other more positive potentials, however. This can be done for instance by replacing the series connection of R₁ and D₁ with a resistive potential divider.

A number of variations in the described circuits are possible within the scope of the present invention. Transistors Q₁ and Q_(A) may be composite transistors comprising respective Darlington cascades of like numbers of transistors. So may Q₂ and Q₃. An emitter follower may replace the direct connection of the collector electrode of Q₁ to the joined emitter electrodes of Q₂ and Q₃ to improve the inverse proportionality of I_(C3) to h_(fel). The provision of current to the collector electrode of Q₁ for I_(C1) to be regulated against can be carried out in a variety of ways known in the art. 

What is claimed is:
 1. In combination:a first, bipolar transistor of a first conductivity type, said first transistor having base and collector electrodes between which a current gain of amplitude h_(fe) is exhibited and having an emitter electrode; means connecting the emitter electrode of said first transistor to a point of fixed potential for referring the emitter potential of said first transistor to said fixed potential; second and third transistors of a second conductivity type complementary to said first conductivity type, each of said second and third transistors having a principal output current conducting path between first and second electrodes thereof and having a control electrode controllable in reference to its said first electrode, said second and third transistors exhibiting effective transconductances proportional to each other; means for maintaining substantially-equal potentials at the control electrodes of said second and third transistors; means for maintaining substantially equal potentials at the first electrodes of said second and third transistors; means for supplying a prescribed current to the collector electrode of said first transistor; means applying collector-to-base feedback to said first transistor for adjusting its emitter-to-base potential to condition said first transistor to conduct at least a portion of said prescribed current, including a direct coupling from the collector electrode of said first transistor to the first electrode of said second transistor, and including a direct coupling from the second electrode of said second transistor to the base electrode of said first transistor; and means for utilizing the current flowing through the second electrode of said third transistor, said current being substantially inversely proportional to h_(fe).
 2. The combination set forth in claim 1 wherein said means for utilizing the collector current of said third transistor includes a fourth, bipolar transistor having a base electrode to which the second electrode of said third transistor is connected and having emitter and collector electrodes biased for normal transistor operation, said fourth transistor exhibiting a current gain of amplitude h_(fe) between its base and collector electrodes, whereby the collector quiescent current of said fourth transistor is proportionally related to said prescribed current.
 3. The combination set forth in claim 1 wherein said means for supplying a prescribed current comprises:means for maintaining a fixed potential between the control electrode of said second transistor and a point of connection; and a resistor connecting the collector electrode of said first transistor to said point of connection.
 4. The combination set forth in claim 1 wherein said means for utilizing the current flowing through the second electrode of said third transistor includes:a fourth, bipolar transistor of the same conductivity type as said first, bipolar transistor, said fourth transistor having base and collector electrodes between which a current gain of amplitude h_(fe) is exhibited and having an emitter electrode; a direct current conductive path from the second electrode of said third transistor to the base electrode of said fourth transistor; and means for connecting said fourth transistor as a common-emitter amplifier for signal, including signal-conductive means connecting the emitter electrode of said fourth transistor to a point of fixed potential for referring the emitter potential of said fourth transistor to said fixed potential.
 5. In combination:first and second transistors of a first conductivity type, each having base and collector electrodes between which a current gain of h_(fe) is exhibited and having an emitter electrode; means for connecting said first transistor as a common-emitter amplifier for signal, which means includes signal-conductive means connecting the emitter electrode of said first transistor to a point of fixed potential for referring the emitter potential of said first transistor to said fixed potential; third and fourth transistors of a second conductivity type complementary to said first conductivity type, each of said third and fourth transistors having a principal output current conducting path between first and second electrodes thereof and having a control electrode controllable in reference to its said first electrode, said third and fourth transistors exhibiting effective transconductances proportional to each other; means for maintaining substantially equal potentials at the control electrodes of said third and fourth transistors; means for maintaining substantially equal potentials at the first electrodes of said third and fourth transistors; means for supplying a prescribed current, connected between the emitter and collector electrodes of said second transistor; means applying collector-to-base feedback to said second transistor for adjusting its emitter-to-base potential to condition said second transistor to conduct at least a portion of said prescribed current, including a direct coupling from the collector electrode of said second transistor to the first electrode of said third transistor, and including a direct coupling from the second electrode of said third transistor to the base electrode of said second transistor; and means connecting the second electrode of said fourth transistor to the base electrode of said first transistor for causing the quiescent current flows through these two electrodes to be substantially equal.
 6. A combination as set forth in claim 5 having:means connecting the emitter electrode of said second transistor to said point of fixed potential for referring said second transistor to said fixed potential. 